1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device having a pipe latch and a semiconductor system including the same.
2. Description of the Related Art
A semiconductor memory device includes a plurality of pipe latches for latching input data, and performs a write operation for aligning and writing the input data in response to a strobe signal DQS. While the semiconductor memory device is performing the write operation, training is performed through a write leveling operation to guarantee that a clock signal and a data strobe signal reach each memory device within an appropriate timing, so that a stable operation is performed.
FIG. 1 is a timing diagram illustrating data training of a conventional semiconductor device.
Referring to FIG. 1, pipe input/output control signals WPIPE_IN<0:1> and WPIPE_OUT<0:1> become fail after abnormal data training.
When the data training is started, a write command 10 is applied and a phase of a data strobe signal DQS is compared with a phase of a clock signal CLK after column address strobe (CAS) write latency (CWL: latency from the input of a write command to the input of write data from outside). At this time, even though an edge of the data strobe signal DQS and an edge of the clock signal CLK are aligned, when the data strobe signal DQS is not inputted in response to the CAS write latency CWL, an abnormal operation occurs in a pipe latch.
FIG. 1 illustrates the case in which the data strobe signal DQS is inputted at a time point (CWL-1) earlier than the CAS write latency CWL by one clock. In this case, the pipe input control signal WPIPE_IN<0> used in the pipe latch becomes fail. Then, even though the data strobe signal DQS corresponding to a subsequently inputted write command 20 is inputted in response to the CAS write latency CWL, the pipe input/output control signals WPIPE_IN<0:1> and WPIPE_OUT<0:1> become fail.
The pipe input/output control signals WPIPE_IN<0:1> and WPIPE_OUT<0:1> are sequentially activated in the data training. That is, the pipe input control signals WPIPE_IN<0:1> are sequentially activated and the pipe output control signals WPIPE_OUT<0:1> are sequentially activated.